Reconsidering the expulsion of routing hardware from BitGrid

I often reconsider the decisions that have lead to the current state of my ideal BitGrid design. This 1999 paper from Tyler J. Moeller at MIT has me reconsidering the expulsion of all routing hardware from the BitGrid.

Specifically, it's page 52 where he lays out a Bit Level Systolic array... and I see that it definitely needs to have more than one bit inbound from some directions.

I've come to realize (since adding Isolinear Memory) that the key property of a BitGrid that makes it valuable is homogeneity, not necessisarily simplicity. If it were possible to add routing for the 4 bits into/out of a cell without loss of generality and homogeneity, it might be an acceptable tradeoff.

Since I'll have two layers of programability in a BitGrid anyway, the LUT values in one control plane, and the configuration in another, routing data via part of the configuration layer shouldn't take too many gates to pull off.

I think this change would allow far more efficient utilization of a BitGrid, but the complexity might not be worth it. I'm open to discussion, should the bus factor for BitGrid ever increase above 1.